Volatile memory resources find widespread usage in current computing platforms, whether for servers, desktop or laptop computers, mobile devices, and consumer and business electronics. DRAM (dynamic random access memory) devices are the most common types of memory devices in use. Volatile memory needs to be refreshed to maintain data in a valid state. However, as memory capacity continues to increase, the time needed to perform a refresh operation (i.e., tRFC) increases. During refresh the memory resources being refreshed are unavailable for read and write accesses. Thus, the increase in refresh time decreases the usable bandwidth in the memory subsystem.
DRAM refresh consumes a large percentage of overall bandwidth. For example, with a 4 Gb DDR4 (dual data rate version 4) die, a refresh command is sent every 7.8 microseconds (us), and each refresh command takes approximately 260 nanoseconds (ns) to complete execution. Thus, refresh consumes approximately 260 ns/7.8 us=5.38% of bandwidth. With the increase to 16 Gb memory devices the number of rows refreshed in response to each command is expected to double to approximately 550 ns for refresh to complete execution, and the time between refreshes is expected to be cut in half to 3.9 us, which results in refresh taking up approximately 550 ns/3.9 us=14.1% of total bandwidth.
A controller initiates a refresh to the DRAM, which ends up locking up the entire rank for the duration of the refresh execution (e.g., 260 ns or 550 ns in accordance with the examples above). Any requests to a DRAM in refresh traditionally have to wait until completion of the refresh. As the refresh execution time increases with increasing memory densities, the probabilities of transactions becoming stalled due to ongoing refreshes increases. Longer refresh times also impact isochronous bandwidth requirements.
Descriptions of certain details and implementations follow, including a description of the figures, which may depict some or all of the embodiments described below, as well as discussing other potential embodiments or implementations of the inventive concepts presented herein.